(1) Field of the Invention
The present invention relates to the field of computer controlled input/output systems, e.g., graphic display systems. More specifically, the present invention relates to methods for controlling input/output data flow within an electronic-system.
(2) Prior Art
Traditionally, the distinctive feature of many input/output devices or xe2x80x9cinput/output unitsxe2x80x9d (e.g., graphics devices) connecting to a host processor has been its random access pattern and its high demand for data. Prior art electronic systems have attempted to facilitate communication of data between a host processor and the input/output unit by placing first-in-first-out (FIFO) buffers within the data transmission path of the input/output data. This is especially true of a graphics unit input/output unit, for example, with respect to graphics data. The buffers function in one way to xe2x80x9csmoothxe2x80x9d out the input/output data traffic into a more uniform data flow and ease communication interfaces between coupled electronic units. In effect, the buffers provide a temporary storage location for the input/output data so that receiving devices need not be ready to receive input/output data at the same instant that sending devices are ready to send and vice-versa. However, in a graphics environment, these buffers can also create side effects that can reduce a computer controlled graphics system""s overall graphics data processing efficiency.
FIG. 1A illustrates an exemplary prior art computer controlled graphics display system 50 that utilizes a buffered communication pathway between the processor and the input/output unit. It is appreciated that a graphics system is exemplary only and that the buffer related problems described herein are also associated with many other more generalized input/output systems. System 50 includes a processor 101 having an internal FIFO buffer 101a coupled to a memory controller 105 which also has an internal FIFO buffer 105a. The memory controller 105 is coupled to a memory unit 102 and also to a data communication bus 100 (which can also contain an internal buffer, not shown). The bus 100 is coupled to a number of optional devices 120 and 122 and also to a graphics unit 1730 which contains an internal FIFO buffer 130a. A dedicated interrupt (IRQ) line 140 is routed from the graphics unit 130 to the memory controller 105. Exemplary sizes of buffers 101a, 105a, and 130a are 128, 256, and 1 k bytes. Assume an internal bus buffer of 512 bytes also exists.
In the configuration of FIG. 1A, the graphics unit 130 contains input/output data flow control circuitry which monitors the level of data contained within its buffer 130a. When the input/output data reaches a certain level, an interrupt is generated by unit 130 over line 140 to inform processor 101 to suspend sending new input/output data until unit 130 can reduce the contents of buffer 130a. The interrupt service routine stops processor 101 from generating more input/output data. When the data level of the buffer 130a is reduced, the invoked interrupt service routine ends and allows processor 101 to resume sending input/output data.
The above input/output data flow control mechanism is problematic due to the number of intermediate buffer devices located between, and including, the processor 101 and the graphics unit 130. These include buffer devices 101a, 105a, and the bus buffer which are all situated between processor 101 and the graphics unit 130. In some prior art systems, additional intermediate buffers can also exist. For instance, the bus 100 can contain multiple buffers, etc. Just after graphics unit 130 generates the buffer full interrupt over line 140, processor 101 suspends generating new input/output data, as discussed above, but any existing input/output data in flight located within each of the above buffers still needs to be moved downstream into the graphics unit 130. Therefore, the graphics unit""s buffer 130a is required to have space to accommodate this additional input/output data after the processor interrupt is invoked.
In prior art systems 50, only a relatively small portion of the input/output buffer 130a is allowed to store input/output data until the interrupt is asserted so that buffer space is available to accommodate the in flight input/output data described above. FIG. 1B illustrates this small portion 151 of buffer 130a. Since the graphics unit 130 does not know whether or not the intermediate buffers contain any input/output data, the remainder portion 153 of buffer 130a is reserved empty to accommodate the size of the processor buffer 101a, the memory controller buffer 105a, any other intermediate buffers 155 (e.g., bus buffer), and an extra buffer 157. The extra buffer 157 is needed to accommodate additional input/output data due to processor skid (e.g., the time or number of cycles it takes the processor to react to an interrupt or flow control signal being asserted), communication latencies, and block input/output data transmissions. Therefore, as seen by FIG. 1B, only a relatively small portion 151 of buffer 130a is actually filled with input/output data before a processor interrupt is needed. In one example, only 128 bytes of the 1 k buffer 103a is used until the processor is interrupted.
By reducing the size of buffer portion 151, the number of processor interrupts increases and the overall efficiency of system 50 decreases. Therefore, the performance of system 50 suffers due to a small buffer portion 151. Increased interrupt frequency can also cause image xe2x80x9cstutteringxe2x80x9d because input/output data flow becomes less uniform. Moreover, since interrupts can be generated in cases where portion 151 is filled, but the intermediate buffers (101a, 105a, bus buffer, etc.) are nevertheless empty, processor 101 can be called upon to enter a lengthy interrupt service routine only to discover that the earlier congestion has since gone away. This again reduces processing efficiency. Since it is not always advantageous to increase the size of buffer 130a due to layout area and cost constraints, what is needed is a system that more efficiently utilizes the amount of buffer storage available within the graphics unit 130. What is further needed is a system that reduces the number of processor interrupts in cases where processor interrupts are not actually warranted.
Accordingly, the present invention provides a computer controlled input/output system that more efficiently controls input/output data flow from a processor to an input/output unit (e.g., a graphics unit). The present invention provides a system that more efficiently utilizes the amount of buffer storage located within an input/output unit before a processor store suspend or interrupt is invoked. Further, the present invention provides a system whereby the number of unnecessary processor interrupts are reduced to increase overall data processing efficiency.
A method and apparatus are described for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit (e.g., a graphics unit) within a computer controlled input/output system (e.g., a graphics display system). The novel system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit (e.g., a graphics unit) having a separate FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data forwarded to the input/output unit, but not yet cleared from the input/output unit""s buffer. These mechanisms regulate input/output data flow to the input/output unit. By placing these mechanisms close to the processor, rather than within the input/output unit, the novel system allows a larger portion of the input/output unit""s buffer to be utilized for storing input/output data before a processor store suspend or processor interrupt is required. This leads to increased input/output data throughput between the processor and the input/output unit by reducing processor interrupts.
The novel system also includes the use of efficient credits to return a value (e.g., from 1 to 255) representative of the number of input/output data processed by the separate input/output unit (e.g., graphics unit). This value is added to the backflow control counter in the coupled devices as appropriate, to keep track of the state of their respective FIFOs. Hence, in accordance with the present embodiment, a single efficient credit can indicate a number of graphics commands (e.g., from 1 to 255). In so doing, the use of such efficient credits greatly reduces the amount of total data transfer bandwidth consumed by the credit return back channel.
The novel system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthy interrupt is required. The above system is particularly useful in conjunction with a graphics input/output unit in a computer controlled graphics display system.
Specifically, embodiments of the present invention include a computer controlled graphics system including an apparatus for controlling flow of input/output data, the apparatus including: a) a processor for generating input/output data, the processor including a processor buffer; b) an input/output unit coupled to receive the input/output data from the processor, the input/output unit for processing the input/output data to render image data, the input/output unit including an internal input/output buffer; and c) a communication bridge coupled between the processor and the input/output unit for transmitting input/output data from the processor to the input/output unit, the communication bridge including a plurality of coupled communication devices wherein individual communication devices contain buffers and wherein a first upstream communication device comprises control circuitry for controlling flow of input/output data from the processor to the input/output unit, the control circuitry including: a counter circuit maintaining a count value, the count value updated upon input/output data sent to the input/output unit from the processor and the count value updated upon credit signals received by the first upstream communication device from the input/output unit, the communication bridge communicating the credit signals; and processor control circuitry for regulating flow of input/output data from the processor to the input/output unit based on the count value of the counter circuit.